Vlsi Lead Asic Design Verification Engineer - Bangalore - Aricent
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VLSI - Contribute to verification environment development. IP, Block, Subsystem and Top level verification and debug
· Experience with SV+UVM/OVM/VMM or Specman/eRM/UVMe · Independently contribute to verification environment development. · Prior experience with assertions, functional coverage & code coverage is desired. · Experience with SOC with C/ASM based tests, Graphics or CPU is an added advantage · Experience with AMS and Power aware verification will be a plus · Good understanding of atleast 2 of these protocols – AXI, AHB, USB, PCIe, DDR, LPDDR, HDMI, MIPI, ethernet. · Excellent interpersonal and analytical skills with the ability to work independently.
Experience (In Month) : 90